Digital hardware architectures for EDGE computing
EDGE-Group
The EDGE group is a research group specialized in designing advanced hardware architectures for edge computing.
In a landscape where data generation increasingly occurs at the edge of the network, our mission is to overcome the latency, bandwidth, and privacy limitations typical of cloud-centric processing. We develop silicon-proven solutions that guarantee top-tier performance, strict energy efficiency, flexibility, and security, bringing artificial intelligence and processing power directly to where data is acquired.
Our research focuses on two main tracks, fully leveraging hardware-software co-design paradigms:
1. Specialized Hardware Acceleration and RISC-V Ecosystem
The open and modular architecture of RISC-V processors is the core of our innovation strategy. We focus on designing and integrating custom accelerators to tailor systems for specific workloads. Our architectural exploration is divided into three main branches:
- Tightly-Coupled Architectures: We design accelerators integrated with the main processor's pipeline. By developing custom Instruction Set Architecture (ISA) extensions, we enable the execution of critical operations with ultra-low latency. This approach is crucial for efficiently accelerating compact neural networks and advanced cryptographic algorithms (such as CRYSTALS-Kyber/Dilithium, ASCON, HQC).
- Loosely-Coupled Architectures: We develop independent coprocessors equipped with direct memory access, optimized for massive and high-throughput data streams. These architectures offload the most demanding tasks from the CPU, finding ideal applications in digital signal processing (DSP), next-generation video coding (AVC, HEVC, VVC), and decoding for telecommunications (convolutional, Turbo, LDPC, and Polar codes), and in AI/Machine Learning for Edge AI applications.
- Near-Memory Computing (All-Digital): We tackle the "memory wall" by creating architectures that move computation logic directly next to the memory. This fully digital paradigm minimizes data transfers on the bus, overcoming the von Neumann bottleneck, and ensuring a drastic reduction in power consumption for battery-powered devices.
2. Hardware Security and Resilience
In edge computing, devices are often deployed in uncontrolled environments. Therefore, we critically analyze vulnerabilities at the physical and architectural levels. We evaluate and enhance system resilience against side-channel attacks (e.g., based on power consumption analysis or electromagnetic emissions) by designing hardware countermeasures capable of guaranteeing the device's root of trust.
The excellence of the EDGE group lies in its ability to master the entire VLSI design cycle, bridging the gap between architectural research and working silicon. We cover the entire flow: from RTL design and logic optimization to physical design (Place & Route), rigorous functional verification, prototyping, and final tapeout. Our solutions are targeted for both FPGA technologies, ideal for rapid prototyping, and ASIC domains, where we maximize Power, Performance, and Area (PPA) optimization.
The group actively collaborates with leading research institutes and industrial partners globally, translating innovation into solutions for highly critical sectors:
- Automotive: High-reliability architectures for V2X communications and autonomous driving.
- Space: High-performance systems for advanced satellite communications.
- Biomedical: Ultra-low-power processors for biosignal analysis on wearable devices.
- Agrifood: Embedded AI systems for monitoring and precision agriculture.
In a landscape where data generation increasingly occurs at the edge of the network, our mission is to overcome the latency, bandwidth, and privacy limitations typical of cloud-centric processing. We develop silicon-proven solutions that guarantee top-tier performance, strict energy efficiency, flexibility, and security, bringing artificial intelligence and processing power directly to where data is acquired.
Our research focuses on two main tracks, fully leveraging hardware-software co-design paradigms:
1. Specialized Hardware Acceleration and RISC-V Ecosystem
The open and modular architecture of RISC-V processors is the core of our innovation strategy. We focus on designing and integrating custom accelerators to tailor systems for specific workloads. Our architectural exploration is divided into three main branches:
- Tightly-Coupled Architectures: We design accelerators integrated with the main processor's pipeline. By developing custom Instruction Set Architecture (ISA) extensions, we enable the execution of critical operations with ultra-low latency. This approach is crucial for efficiently accelerating compact neural networks and advanced cryptographic algorithms (such as CRYSTALS-Kyber/Dilithium, ASCON, HQC).
- Loosely-Coupled Architectures: We develop independent coprocessors equipped with direct memory access, optimized for massive and high-throughput data streams. These architectures offload the most demanding tasks from the CPU, finding ideal applications in digital signal processing (DSP), next-generation video coding (AVC, HEVC, VVC), and decoding for telecommunications (convolutional, Turbo, LDPC, and Polar codes), and in AI/Machine Learning for Edge AI applications.
- Near-Memory Computing (All-Digital): We tackle the "memory wall" by creating architectures that move computation logic directly next to the memory. This fully digital paradigm minimizes data transfers on the bus, overcoming the von Neumann bottleneck, and ensuring a drastic reduction in power consumption for battery-powered devices.
2. Hardware Security and Resilience
In edge computing, devices are often deployed in uncontrolled environments. Therefore, we critically analyze vulnerabilities at the physical and architectural levels. We evaluate and enhance system resilience against side-channel attacks (e.g., based on power consumption analysis or electromagnetic emissions) by designing hardware countermeasures capable of guaranteeing the device's root of trust.
The excellence of the EDGE group lies in its ability to master the entire VLSI design cycle, bridging the gap between architectural research and working silicon. We cover the entire flow: from RTL design and logic optimization to physical design (Place & Route), rigorous functional verification, prototyping, and final tapeout. Our solutions are targeted for both FPGA technologies, ideal for rapid prototyping, and ASIC domains, where we maximize Power, Performance, and Area (PPA) optimization.
The group actively collaborates with leading research institutes and industrial partners globally, translating innovation into solutions for highly critical sectors:
- Automotive: High-reliability architectures for V2X communications and autonomous driving.
- Space: High-performance systems for advanced satellite communications.
- Biomedical: Ultra-low-power processors for biosignal analysis on wearable devices.
- Agrifood: Embedded AI systems for monitoring and precision agriculture.
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Scientific coordinator
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Research team
Research area
Research topics
- Design and implementation of hardware accelerators for artificial intelligence in the RISC-V ecosystem.
- Design and implementation of programmable near-memory computing architectures.
- Design and implementation of hardware accelerators for post-quantum cryptography in the RISC-V ecosystem.
- Evaluation of side-channel attacks resilience of hardware systems and design of countermeasures.